The present invention relates generally to the fabrication of integrated circuits and, more particularly, relates to the fabrication of integrated circuits by a patterning process which uses self-assembling polymers.
The semiconductor industry has a need to manufacture integrated circuits (ICs) with higher and higher densities of devices on a smaller chip area to achieve greater functionality and to reduce manufacturing costs. This desire for large-scale integration has led to a continued shrinking of the circuit dimensions and features of the devices.
The ability to reduce the sizes of structures such as gates in field effect transistors (FETs), is driven by lithographic technology which is, in turn, dependent upon the wavelength of light used to expose the photoresist. In current commercial fabrication processes, optical devices expose the photoresist using light having a wavelength of 193 nm (nanometers). Research and development laboratories are experimenting with the EUV (13 nm) wavelength to reduce the size of structures. Further, advanced lithographic technologies are being developed that utilize immersion techniques to improve resolution.
A challenge facing lithographic technology is fabricating features having a critical dimension (CD) below 50 nm. All steps of the photolithographic techniques currently employed must be improved to achieve the further reduction in feature size.
In a conventional lithography technique, light is exposed through a binary mask to a photoresist layer on a layer of material. The photoresist layer may be either a positive or a negative photoresist and can be a silicon-containing, dry-developed resist. In the case of a positive photoresist, the light causes a photochemical reaction in the photoresist. The photoresist is removable with a developer solution at the portions of the photoresist that are exposed through the mask. The photoresist is developed to clear away these portions, whereby a photoresist feature remains on the layer of material. An integrated circuit feature, such as a gate, via, or interconnect, is then etched into the layer of material, and the remaining photoresist is removed.
The line-width of the integrated circuit feature is limited using the conventional lithography process. For example, aberrations, focus, and proximity effects in the use of light limit the ability to fabricate features having reduced linewidth. Using a 248 nm wavelength light source, the minimum printed feature linewidth is between 300 and 150 nm, using conventional techniques. The most advanced lithography tools can now resolve to 100 nm feature size which can be improved to 70 to 80 nm with immersion lithography. With IC design expected to require sub-50 nm interconnects, it is apparent that conventional lithography cannot meet this design requirement.
Accordingly there is a need for reducing the IC interconnect opening diameter to below the resolutions of the conventional lithographic tools, to improve circuit layout density.